AS4C512M16D3LB-12BINTR

Alliance Memory
913-4C51216D3LB12BIT
AS4C512M16D3LB-12BINTR

Mfr.:

Description:
DRAM DDR3L, 8G, 512M X 16, 1.35V, 96-BALL FBGA, 800MHZ INDUSTRIAL TEMPTAPE AND REEL, B Die (MT41K512M16HA-125IT:A)

ECAD Model:
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Availability

Stock:
Non-Stocked
Factory Lead Time:
16 Weeks Estimated factory production time.
Minimum: 2000   Multiples: 2000
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
This Product Ships FREE

Pricing (EUR)

Qty. Unit Price
Ext. Price
Full Reel (Order in multiples of 2000)
58,55 € 117.100,00 €

Product Attribute Attribute Value Select Attribute
Alliance Memory
Product Category: DRAM
RoHS:  
SDRAM - DDR3L
8 Gbit
16 bit
800 MHz
FBGA-96
512 M x 16
20 ns
1.283 V
1.45 V
- 40 C
+ 95 C
AS4C512M16D3LB-12
Reel
Brand: Alliance Memory
Country of Assembly: TW
Country of Diffusion: TW
Country of Origin: TW
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 2000
Subcategory: Memory & Data Storage
Supply Current - Max: 122 mA
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Attributes selected: 0

USHTS:
8542320036
ECCN:
EAR99

DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features, and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source synchronous fashion. These Alliance Memory devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface that transfers two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Alliance Memory DDR3L SDRAM is available in various package sizes.