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IS43R83200D-6TLI

Name: ISSI IS43R83200D-6TLI
Brand: ISSI
SKU: 870-IS43R83200D-6TLI
Price: 7.19 EUR
Availability: OutOfStock

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Mouser No:

870-IS43R83200D-6TLI

Mfr. No:

IS43R83200D-6TLI

Mfr.:

ISSI

Description:

DRAM 256M, 2.5V, DDR, 32Mx8, 166MHz, 66 pin TSOP II (400 mil) RoHS, IT

Datasheet:

IS43R83200D-6TLI Datasheet (PDF)

ECAD Model:

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Learn more about ISSI IS43R83200D-6TLI

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Pricing (EUR)

Qty.	Unit Price	Ext. Price
	7,19 €	7,19 €
	6,69 €	66,90 €
	6,48 €	162,00 €
	6,33 €	316,50 €
	6,01 €	649,08 €
	5,99 €	1.293,84 €
	5,90 €	3.186,00 €
	5,82 €	6.285,60 €
2.592	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	ISSI
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR
Memory Size:	256 Mbit
Data Bus Width:	8 bit
Maximum Clock Frequency:	166 MHz
Package/Case:	TSOP-II-66
Organisation:	32 M x 8
Access Time:	6 ns
Supply Voltage - Min:	2.3 V
Supply Voltage - Max:	2.7 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Series:	IS43R83200D
Packaging:	Tray
Brand:	ISSI
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	CN
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	108
Subcategory:	Memory & Data Storage
Supply Current - Max:	280 mA

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Datasheet

IS43R83200D-6TLI Datasheet (PDF)

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CNHTS:: 8542319090
USHTS:: 8542320024
JPHTS:: 854232021
KRHTS:: 8542321010
MXHTS:: 8542320201
ECCN:: EAR99

IS43R32800D 8Mx32 256-Mbit DDR SDRAM

ISSI IS43R32800D 8Mx32 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64MB to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages.

DDR SDRAM

ISSI 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages. The device is available in 8-bit, 16-bit, and 32-bit data word sizes. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. ISSI 512-Mbit DDR SDRAM commands are registered on the positive edges of CLK.