IS46LR16320C-6BLA1

ISSI
870-I46LR16320C6BLA1
IS46LR16320C-6BLA1

Mfr.:

Description:
DRAM Automotive (-40 to +85C), 512M, 1.8V, Mobile DDR, 32Mx16, 60 ball BGA (8mmx10mm) RoHS

ECAD Model:
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Availability

Stock:
Non-Stocked
Factory Lead Time:
16 Weeks Estimated factory production time.
Minimum: 300   Multiples: 300
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
This Product Ships FREE

Pricing (EUR)

Qty. Unit Price
Ext. Price
6,45 € 1.935,00 €
6,27 € 3.762,00 €
6,19 € 7.428,00 €
2.700 Quote

Product Attribute Attribute Value Select Attribute
ISSI
Product Category: DRAM
RoHS:  
SDRAM - DDR
512 Mbit
16 bit
166 MHz
BGA-60
32 M x 16
6 ns
1.7 V
1.95 V
- 40 C
+ 85 C
IS46LR16320C
Tray
Brand: ISSI
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: CN
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 300
Subcategory: Memory & Data Storage
Supply Current - Max: 60 mA
Tradename: PowerSaver
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CNHTS:
8542319090
USHTS:
8542320028
JPHTS:
854232021
MXHTS:
8542320201
ECCN:
EAR99

Mobile DDR SDRAM

ISSI Mobile DDR SDRAM is organized as 4 banks of 16,777,216 words x 16 bits and uses a double-data-rate architecture to achieve high-speed operation. The Data Input/Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. ISSI Mobile DDR SDRAM offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

IS43LR16800F 2Mx16 Mobile DDR SDRAM

ISSI IS43LR16800F 2Mx16 Mobile DDR SDRAM is 134,217,728 bits Mobile Double Data Rate (DDR) Synchronous DRAM (SDRAM) organized as 4 banks of 2,097,152 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.